The basic technological concept of the present invention is related to a spatial orientation of the individual nanotubes during the process of their electrophoretic deposition on the appropriately chosen metal electrodes. This simple and economical method of control of the nanotube placement can be used for making a mass production technology for nanotube-based electronic and photonic devices.
Carbon nanotubes (CNT) possess unique properties that make them great candidates for future novel high-speed, high efficiency electronic and photonic devices. These properties include: two-dimensional quantization of the energy spectrum (quantum size effect), ballistic electron propagation along the tube, current densities as high as 109 A/cm2 (vs. 106 A/cm2 in Si FET channel), existence of a semiconductor phase, possibilities for n- and p-doping with a high carrier mobility, as well as excellent thermal conductance, make the CNT-based devices an excellent material for the future replacement of the Si-based electronics. All these semiconductor features are characteristic of specific, Single Walled CNT (SWNT), and only these nanotubes will be used in the proposed invention.
In addition, the optically active, direct interband and intraband photon transitions, make the nanotubes a strong contender to III-V optoelectronic devices. Furthermore, when made on a Si wafer, CNT can produce a combination of electronic and optoelectronic circuits combined with Si electronics, thus making hybrid electron and photonic circuits on the Si wafer.
The key element widely used in the electronic logic circuits is voltage inverter (CMOS), wherein both switching states consume minimum energy. It is vitally important for future development of electronics beyond the Si world to mass produce such an element using CNT technology. The attempts to build CNT inverter have been carried out in many research places worldwide. Typically, it is made from nanotubes extended between source and drain metal contacts deposited on the Si substrate, while the controlling gate electrode is made simply by placing the nanotube on top of the SiO2 insulating layer grown on the n+ Si substrate. Such a design is utilized in essentially all publication on this topic, for both inverter circuit and individual transistors. The drawback of this method is its impracticality for any scale of circuit integration: placement of multiple identical nanotubes to enhance the output current or to form new circuit elements requires a special micro-manipulator and thus precludes any possibility of IC mass manufacturing. Another problem related to placement of the nanotubes onto SiO2/n+Si base is existence of only one gate electrode common to all the nanotubes involved, namely, the n+Si wafer separated from the nanotubes by an oxide dielectric.
Another technology of making SWCNT arrays comes from the nanotube vertical growth in the CVD process, see e.g. A. Kastalsky U.S. Pat. No. 7,851,784. This method however requires formation of extremely small pads of catalytic material of less than 5 nm in diameter which is unachievable even for e-beam lithography. Different methods of further reducing the catalytic metal pad area are considered (see e.g. A. Kastalsky, US Patent Application #20110186808, or A. Kastalsky U.S. patent application Ser. No. 13/401,220, filed Feb. 21, 2012). The future success of CNT devices will rely on emergence of new and simple manufacturing processes which both provide a good control of the nanotube placement, orientation and uniformity of their properties and ensure a high-yield, large volume production and cost efficiency above the modern electronic and photonic semiconductor technologies.